Technical Field
The present invention generally relates to parasitic capacitance reduction in semiconductor devices. More particularly, the present invention relates to source and drain parasitic capacitance reduction in FinFET-based semiconductor structures having tucked fins.
Background Information
In the semiconductor industry, there is pressure to constantly improve the speed of semiconductor devices. For example, the market demands improvement in the speed of semiconductor memory and logic circuits. However, such memory and logic circuits need to reduce parasitic capacitance at the source and drain if they are to increase the speed of operation.
Thus, a need continues to exist for ways to reduce parasitic capacitance at the source/drain in memory/logic circuits.